TSL2569T【PDF 6/37 页】IC LIGHT TO DGTL CONV 6-TMB

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Sheet目录58

2页 3页 4页 5页 [6页]7页 8页 9页 10页

TSL2568, TSL2569

LIGHT-TO-DIGITAL CONVERTER

TAOS091D DECEMBER 2008

The LUMENOLOGY r Company

www.taosinc.com

NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs

and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.

3. The 640 nm irradiance E

is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength

籶 = 640 nm and spectral halfwidth 敾?= 17 nm.

4. The 940 nm irradiance E

is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength

籶 = 940 nm and spectral halfwidth 敾?= 40 nm.

5. Integration time T

int

, is dependent on internal oscillator frequency (f

osc

) and on the integration field value in the timing register as

described in the Register Set section. For nominal f

osc

= 735 kHz, nominal T

int

= (number of clock cycles)/f

osc

Field value 00: T

int

= (11 ?/SPAN> 918)/f

osc

= 13.7 ms

Field value 01: T

int

= (81 ?/SPAN> 918)/f

osc

= 101 ms

Field value 10: T

int

= (322 ?/SPAN> 918)/f

osc

= 402 ms

Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),

and 322/322 = 1 (field value 10).

6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also

by a 2-count offset.

Full scale ADC count value = ((number of clock cycles)/2 2)

Field value 00: Full scale ADC count value = ((11 ?/SPAN> 918)/2 2) = 5047

Field value 01: Full scale ADC count value = ((81 ?/SPAN> 918)/2 2) = 37177

Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached

for 131074 clock cycles, which occurs for T

int

= 178 ms for nominal f

osc

= 735 kHz.

7. Low gain mode has 16y lower gain than high gain mode: (1/16 = 0.0625).

8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC

count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual

Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with

fluorescent or incandescent light sources.

AC Electrical Characteristics, V

= 3 V, T

= 255C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(CONV)

Conversion time

100

400

Clock frequency (I

C only)

400

kHz

(SCL)

Clock frequency (SMBus only)

100

kHz

(BUF)

Bus free time between start and stop condition

1.3

約

(HDSTA)

Hold time after (repeated) start condition. After

this period, the first clock is generated.

0.6

約

(SUSTA)

Repeated start condition setup time

0.6

約

(SUSTO)

Stop condition setup time

0.6

約

(HDDAT)

Data hold time

0.9

約

(SUDAT)

Data setup time

100

(LOW)

SCL clock low period

1.3

約

(HIGH)

SCL clock high period

0.6

約

(TIMEOUT)

Detect clock/data low timeout (SMBus only)

Clock/data fall time

300

Clock/data rise time

300

Input pin capacitance

Specified by design and characterization; not production tested.

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